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AS6C3216 rev. 1 .0 32m bits ( 2mx 16 / 4mx8 switchable) low power cmos sram alliance memory, inc . 0 revision history revision description issue date rev. 1.0 initial issue sep . 06 .20 1 2
AS6C3216 rev. 1 .0 32m bits ( 2mx 16 / 4mx8 switchable) low power cmos sram alliance memory, inc . 1 features ? fast access time : 55 ns ? low power consumption: operating current : 45 ma ( typ . ) standby current : 10 ? a ( typ . ) s l - version ? singl e 2.7v ~ 3.6v power supply ? all inputs and outputs ttl compatible ? fully static operation ? tr i - state output ? data byte control : (i) byte# fixed to v cc lb# controlled dq0 ~ dq7 ub# controlled d q8 ~ dq15 (ii) byte# fixed to v ss dq15 used as addre ss pin, while lb#, ub# and dq8~dq14 pins not used ? data retention voltage : 1. 2 v ( min .) ? g reen p ackage available ? package : 4 8 - pin 12mm x 20mm tsop - i general description the AS6C3216 is a 33,554,432 - bit low power cmos static random access mem ory organized as 2,097,152 words by 16 bits or 4,194,304 words by 8 bits . it is fabricated using very high performance, high reliability cmos technology. its standby current is stable within the range of operating temperature. the AS6C3216 is well designe d for low power application, and particularly well suited for battery back - up nonvolatile memory application. the AS6C3216 operates from a single power supply of 2.7v ~ 3.6v and all inputs and outputs are fully ttl compatible product family produ ct family operating temperature vcc range speed power dissipation standby( i sb1, typ.) operating( icc,typ.) AS6C3216 (i) - 4 0 ~ 85
AS6C3216 rev. 1 .0 32m bits ( 2mx 16 / 4mx8 switchable) low power cmos sram alliance memory, inc . 2 functional block diagram pin description symbol description a0 C C C cc power supply v ss ground control circuit decoder 2048 kx 16 / 4096 kx 8 memory array column i / o a 0 ~ a 20 / a - 1 ~ a 20 vcc vss dq 8 - dq 15 upper byte dq 0 - dq 7 lower byte i / o data circuit ce 2 we # oe # lb # ub # ce # byte #
AS6C3216 rev. 1 .0 32m bits ( 2mx 16 / 4mx8 switchable) low power cmos sram alliance memory, inc . 3 pin configuration absolute maximun ratings * parameter symbol rating unit voltage on v cc relative to v ss v t 1 - 0.5 to 4.6 v voltage on any other pin relative to v ss v t 2 - 0.5 to v cc +0.5 v operating temperature t a - 4 0 to 85(i grade) stg - 65 to 150 d 1 w dc output current i out 50 ma *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stre ss rating only and functional ope ration of the device or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect device reliab ility. tsop - i a 15 a 14 a 13 a 12 a 8 as 6 c 3216 8 7 6 5 4 3 2 1 a 11 a 10 a 9 a 20 a 19 we # ce 2 nc ub # lb # a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 14 13 12 11 10 9 16 15 22 21 20 19 18 17 24 23 dq 13 byte # dq 15 / a - 1 dq 7 dq 14 dq 6 44 41 42 43 a 16 vss 48 47 45 46 33 36 35 34 38 39 40 37 25 28 27 26 30 31 32 29 dq 12 dq 5 dq 4 vcc dq 11 dq 3 dq 10 dq 2 dq 1 dq 9 dq 8 dq 0 oe # vss ce # a 0
AS6C3216 rev. 1 .0 32m bits ( 2mx 16 / 4mx8 switchable) low power cmos sram alliance memory, inc . 4 truth table mode c e# c e2 byte# oe# we# lb# ub# i/o operation supply current dq0 - dq7 dq8 - dq1 4 dq15 standby h x x x l x x x h x x x x x x x x h x x h high C C C C C C C C C sb , i sb1 output disable l l l h h h h h l h h h h h h l x x x l x high C C C C C C C C C cc ,i cc1 read l l l h h h h h h l l l h h h l h l h l l d out high C out high C out d out high C out d out i cc ,i cc1 write l l l h h h h h h x x x l l l l h l h l l d in high C in high C in d in high C in d in i cc ,i cc1 byte# read l h l l h x x dout high C cc ,i cc1 byte # write l h l x l x x din high C cc ,i cc1 note: h = v ih , l = v il , x = don't care. dc electrical cha racteristics parameter symbol test condition min. typ. * 4 max. unit supply voltage v cc 2.7 3. 0 3.6 v input high voltage v ih *1 2. 2 - v cc +0. 3 v input low voltage v il *2 - 0. 2 - 0.6 v input leakage current i li v cc R v in R v ss - 1 - 1 a output leakage c urrent i lo v cc R v out R v ss output disabled - 1 - 1 a output high voltage v oh i oh = - 1ma 2. 2 2.7 - v output low voltage v ol i ol = 2 ma - - 0.4 v average operating power supply current i cc cycle ti me = min. ce# = v il and ce2 = v ih i i/o = 0ma o ther pins at v il or v ih - 5 5 - 45 80 ma i cc1 cycle time = 1 s ce# Q 0.2v and ce2 R v cc - 0.2v i i/o = 0ma o ther pins at 0.2v or v cc - 0.2v - 10 20 ma standby power supply current i sb ce# = v ih or ce2 = v il o ther pins at v i l or v i h - 0.3 2 m a i sb1 ce# R v cc - 0.2v or ce2 Q 0.2v o ther pins at 0.2v or v cc - 0.2v - sli - 10 120 a notes: 1. v ih (max) = v cc + 3.0 v for pulse width less than 10ns. 2. v il (min) = v ss - 3.0 v for pulse widt h less than 10ns. 3. over/undershoot specifications are characterized, not 100% tested. 4 . typical values are included for reference only and are not guaranteed or tested. typical value s are measured at v cc = v cc (typ.) and t a = 25
AS6C3216 rev. 1 .0 32m bits ( 2mx 16 / 4mx8 switchable) low power cmos sram alliance memory, inc . 5 capacitance (t a = 25 parameter symbol min. max unit input capacitance c in - 6 pf input/output capacitance c i/o - 8 pf note : these parameters are guaranteed by device characterization, but not production tested. ac test conditions input pulse levels 0 .2 v to v cc - 0.2 v input rise and fall times 3 ns input and output timing reference levels 1.5v output load c l = 3 0pf + 1ttl , i oh /i ol = - 1ma/ 2 ma ac electrical characteristics (1) read cycle parameter sym . AS6C3216 - 55 unit min. max. read cycle time t rc 5 5 - ns address access time t aa - 55 ns chip enable access time t ace - 55 ns output enable access time t oe - 30 ns chip enable to output in low - z t clz * 10 - ns output enable to output in low - z t olz * 5 - ns chip disable to output in high - z t chz * - 20 n s output disable to output in high - z t ohz * - 20 ns output hold from address change t oh 10 - ns lb#, ub# a c cess time t ba - 55 ns lb#, ub# to high - z output t bhz * - 25 n s lb#, ub# to low - z output t blz * 10 - ns (2) write cycle parameter sym . AS6C3216 - 5 5 unit min. max. write cycle time t wc 55 - ns address valid to end of write t aw 50 - ns chip enable to end of write t cw 50 - ns address set - up time t as 0 - ns write pulse width t wp 45 - ns write recovery time t wr 0 - ns data to write time overla p t dw 25 - ns data hold from end of write time t dh 0 - ns output active from end of write t ow * 5 - ns write to output in high - z t whz * - 2 0 ns lb#, ub# valid to end of write t b w 45 - ns *these parameters are guaranteed by device characterization, but n ot production tested.
AS6C3216 rev. 1 .0 32m bits ( 2mx 16 / 4mx8 switchable) low power cmos sram alliance memory, inc . 6 t iming waveforms read cycle 1 (address controlled) (1,2) read cycle 2 ( ce# and ce2 and oe# controlled) (1,3,4,5) notes : 1. we# is high for read cycle. 2.device is contin uously selected oe# = low , ce# = low, ce2 = high, lb# or ub# = low . 3.address must be valid prior to or coincident with ce# = low, ce2 = high, lb# or ub# = low transition; otherwise t aa is the limiting parameter. 4.t clz , t blz, t olz , t chz, t bhz and t ohz are specified with c l = 5pf. transition is measured 500mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t bhz is less than t blz , t ohz is less than t olz . dout data valid t oh t aa address t rc previous data valid dout data valid high - z high - z t clz t olz t chz t ohz t oh oe # t oe lb #, ub # t bhz t ace t ba t blz ce # t aa address t rc ce 2
AS6C3216 rev. 1 .0 32m bits ( 2mx 16 / 4mx8 switchable) low power cmos sram alliance memory, inc . 7 write cycle 1 ( we# controlled) (1,2,3,5,6) write cycle 2 ( ce# and ce2 c ontrolled) (1,2,5,6) dout din data valid t d w t d h ( 4 ) high - z t whz we # t wp t cw t wr t as ( 4 ) t ow lb #, ub # t bw ce # t aw address t wc ce 2 dout din data valid t d w t d h ( 4 ) high - z t whz we # lb #, ub # t cw t wp t bw ce # address t wr t as t aw t wc ce 2
AS6C3216 rev. 1 .0 32m bits ( 2mx 16 / 4mx8 switchable) low power cmos sram alliance memory, inc . 8 write cycle 3 ( lb# , ub# controlled) (1,2,5 ,6 ) notes : 1. we#,ce#, lb#, ub# must be high or ce2 must be low during all a ddress transitions. 2.a write occurs during the overlap of a low ce#, high ce2, low we#, lb# or ub# = low. 3.during a we# controlled write cycle with oe# low , t wp must be greater than t whz + t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the output state, and input signals must not be applied. 5.if the ce#, lb#, ub# low transition and ce2 high transition occurs simultaneously with or after we# low transition, the outputs remain in a high impedanc e state. 6.t ow and t whz are specified with c l = 5pf. transition is measured 500mv from steady state. dout din data valid t d w t d h ( 4 ) high - z t whz we # lb #, ub # t cw t as t wp t bw ce # address t wr t aw t wc ce 2
AS6C3216 rev. 1 .0 32m bits ( 2mx 16 / 4mx8 switchable) low power cmos sram alliance memory, inc . 9 data retention characteristics parameter symbol test condition min. typ. max. unit v cc for data retention v dr ce# R v cc - 0.2v or ce2 Q 0.2v 1. 2 - 3.6 v data retention current i dr v cc = 1. 2 v ce# R v cc - 0.2v or ce2 Q 0.2v other pins at 0.2v or v cc - 0.2v - s l - 8 80 a - s li - 8 120 a chip disable to data retention time t cdr see data retention waveforms (below) 0 - - ns recovery time t r t rc * - - ns t rc * = read cycle time data retention waveform low vcc data retention waveform (1) ( ce# controlled) low vcc data retention waveform (2) ( ce 2 controlled) low vcc data retention waveform ( 3 ) ( lb# , ub# controlled) vcc ce # v dr ? 1 . 2 v ce # ? v cc - 0 . 2 v v cc ( min .) v ih t r t cdr v ih v cc ( min .) vcc ce 2 v dr ? 1 . 2 v ce 2 ?? 0 . 2 v v cc ( min .) v i l t r t cdr v i l v cc ( min .) vcc lb #, ub # v dr ? 1 . 2 v lb #, ub # ? v cc - 0 . 2 v v cc ( min .) v ih t r t cdr v ih v cc ( min .)
AS6C3216 rev. 1 .0 32m bits ( 2mx 16 / 4mx8 switchable) low power cmos sram alliance memory, inc . 10 package outline dimension 4 8 - pin 12mm x 20mm tsop - i package outline dimension
AS6C3216 rev. 1 .0 32m bits ( 2mx 16 / 4mx8 switchable) low power cmos sram alliance memory, inc . 11 ordering information allia nce organization vcc range package operating temp speed ns AS6C3216 - 55tin 2050 x 16 2.7v C 3.6 v 48pin tsop i industrial ~ - 40c - 85c 55
AS6C3216 rev. 1 .0 32m bits ( 2mx 16 / 4mx8 switchable) low power cmos sram alliance memory, inc . 12 this page is left blank intentionally.

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